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HM5112805 Series, HM5113805 Series
128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh
ADE-203-839C (Z) Rev. 2.0 Jul. 10, 1998 Description
The Hitachi HM5112805 Series, HM5113805 Series are 128M-bit dynamic RAMs organized as 16,777,216-word x 8-bit. They have realized high performance and low power by employing CMOS process technology. HM5112805 Series, HM5113805 Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They are packaged in 32-pin plastic TSOPII.
Features
* Single 3.3 V supply: 3.3 V 0.3 V * Access time: 60 ns (max) * Power dissipation Active: 720 mW (max) (HM5112805 Series) 792 mW (max) (HM5113805 Series) Standby : 3.6 mW (max) (CMOS interface) : 1.8 mW (max) (CMOS interface) (L-version) * EDO page mode capability * Refresh cycles #$-only refresh 8192 cycles/64 ms (HM5112805 Series) 4096 cycles/64 ms (HM5113805 Series) CBR/Hidden refresh 4096 cycles/64 ms (HM5112805 Series, HM5113805 Series)
HM5112805 Series, HM5113805 Series
* 4 variations of refresh #$-only refresh $-before-#$ refresh Hidden refresh Self refresh (L-version) * Battery backup operation (L-version)
Ordering Information
Type No. HM5112805TD-6 HM5112805LTD-6 HM5113805TD-6 HM5113805LTD-6 Access time 60 ns 60 ns 60 ns 60 ns Package 400-mil 32-pin plastic TSOP II (TTP-32DF)
2
HM5112805 Series, HM5113805 Series
Pin Arrangement (HM5112805 Series)
32-pin TSOP VCC I/O0 I/O1 I/O2 I/O3 NC VCC WE RAS A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS I/O7 I/O6 I/O5 I/O4 VSS CAS OE A12 A11 A10 A9 A8 A7 A6 VSS
Pin Description
Pin name A0 to A12 Function Address input * * I/O0 to I/O7 Row/Refresh address Column address A0 to A12 A0 to A10
Data input/output Row address strobe Column address strobe Write enable Output enable Power supply Ground No connection
5$6 &$6 :( 2(
VCC VSS NC
3
HM5112805 Series, HM5113805 Series
Pin Arrangement (HM5113805 Series)
32-pin TSOP VCC I/O0 I/O1 I/O2 I/O3 NC VCC WE RAS A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS I/O7 I/O6 I/O5 I/O4 VSS CAS OE NC A11 A10 A9 A8 A7 A6 VSS
Pin Description
Pin name A0 to A11 Function Address input * * I/O0 to I/O7 Row/Refresh address Column address A0 to A11 A0 to A11
Data input/output Row address strobe Column address strobe Write enable Output enable Power supply Ground No connection
5$6 &$6 :( 2(
VCC VSS NC
4
HM5112805 Series, HM5113805 Series
Block Diagram (HM5112805 Series)
A0 A1 to A10 * * * Column address buffers
Column decoder 16M array
Upper pellet
Row decoder
16M array I/O buffers 16M array
Row address buffers A11 A12
I/O1 I/O3 I/O4 I/O6
16M array
Timing and control
RAS
CAS
WE
OE Lower pellet
Timing and control
Column decoder Column address buffers 16M array
Row decoder
16M array I/O buffers 16M array
* * *
Row address buffers
I/O0 I/O2 I/O5 I/O7
16M array
5
HM5112805 Series, HM5113805 Series
Block Diagram (HM5113805 Series)
A0 A1 to A10 * * * Column address buffers
Column decoder 16M array
Upper pellet
Row decoder
16M array I/O buffers 16M array
Row address buffers A11
I/O1 I/O3 I/O4 I/O6
16M array
Timing and control
RAS
CAS
WE
OE Lower pellet
Timing and control
Column decoder Column address buffers 16M array
Row decoder
16M array I/O buffers 16M array
* * *
Row address buffers
I/O0 I/O2 I/O5 I/O7
16M array
6
HM5112805 Series, HM5113805 Series
Operation Table
5$6
H L L L L L H to L L
&$6
x L L L L H L L
:(
x H L* L* x H H
2 2
2(
x L x H L to H x x H
I/O 0 to I/O 7 High-Z Dout Din Din Dout/Din High-Z High-Z High-Z
Operation Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle
H to L
5$6-only refresh cycle &$6-before-5$6 refresh cycle
Read cycle (Output disabled)
Notes: 1. H: VIH (inactive), L: VIL (active), x: VIH or VIL 2. tWCS 0 ns: Early write cycle tWCS < 0 ns: Delayed write cycle
Absolute Maximum Ratings
Parameter Terminal voltage on any pin relative to VSS Power supply voltage relative to VSS Short circuit output current Power dissipation Storage temperature Symbol VT VCC Iout PT Tstg Value -0.5 to VCC + 0.5 ( 4.6 V (max)) -0.5 to +4.6 50 1.0 -55 to +125 Unit V V mA W C
DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range VIH VIL Ta Min 3.0 0 2.0 -0.3 0 Typ 3.3 0 -- -- -- Max 3.6 0 VCC + 0.3 0.8 70 Unit V V V V _C Notes 1, 2 2 1 1
Notes: 1. All voltage referred to VSS. 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
7
HM5112805 Series, HM5113805 Series
DC Characteristics (HM5112805 Series)
HM5112805 -6 Parameter Operating current* * Standby current
1, 2
Symbol ICC1 ICC2
Min -- --
Max 200 4
Unit mA mA
Test conditions tRC = min
5$6, &$6 = V
Dout = High-Z
TTL interface
IH
--
1
mA
5$6, &$6 V
Dout = High-Z
CMOS interface
CC
- 0.2 V
Standby current (L-version)
ICC2
--
500
A
5$6, &$6 V
Dout = High-Z tRC = min
CMOS interface
CC
- 0.2 V
5$6-only refresh current*
Standby current*
1
2
ICC3 ICC5 ICC6 ICC7 ICC10
-- -- -- -- --
200 10 200 200 2
mA mA mA mA mA
5$6 = VIH, &$6 = VIL Dout = enable
tRC = min
&$6-before-5$6 refresh current
EDO page mode current* * Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
4 1, 3
5$6 = VIL , &$6 cycle, tHPC = tHPC min
CMOS interface Dout = High-Z CBR refresh: tRC = 15.6 s tRAS 0.3 s
ICC11
--
1.6
mA
5$6, &$6 0.2 V
Dout = High-Z 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
CMOS interface
ILI ILO VOH VOL
-5 -5 2.4 0
5 5 VCC 0.4
A A V V
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while 5$6 = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
8
HM5112805 Series, HM5113805 Series
DC Characteristics (HM5113805 Series)
HM5113805 -6 Parameter Operating current* * Standby current
1, 2
Symbol ICC1 ICC2
Min -- --
Max 220 4
Unit mA mA
Test conditions tRC = min
5$6, &$6 = V
Dout = High-Z
TTL interface
IH
--
1
mA
5$6, &$6 V
Dout = High-Z
CMOS interface
CC
- 0.2 V
Standby current (L-version)
ICC2
--
500
A
5$6, &$6 V
Dout = High-Z tRC = min
CMOS interface
CC
- 0.2 V
5$6-only refresh current*
Standby current*
1
2
ICC3 ICC5 ICC6 ICC7 ICC10
-- -- -- -- --
220 10 220 200 2
mA mA mA mA mA
5$6 = VIH, &$6 = VIL Dout = enable
tRC = min
&$6-before-5$6 refresh current
EDO page mode current* * Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
4 1, 3
5$6 = VIL , &$6 cycle, tHPC = tHPC min
CMOS interface Dout = High-Z CBR refresh: tRC = 15.6 s tRAS 0.3 s
ICC11
--
1.6
mA
5$6, &$6 0.2 V
Dout = High-Z 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
CMOS interface
ILI ILO VOH VOL
-5 -5 2.4 0
5 5 VCC 0.4
A A V V
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while 5$6 = VIL. 3. Measured with one sequential address change per EDO cycle, tHPC. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
9
HM5112805 Series, HM5113805 Series
Capacitance (Ta = 25_C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 7 7 8 Unit pF pF pF Notes 1 1 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. 5$6 and &$6 = VIH to disable Dout.
10
HM5112805 Series, HM5113805 Series
AC Characteristics (Ta = 0 to +70_C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *2, *19
Test Conditions * * * * * Input rise and fall time: 2 ns Input pulse levels: VIL = 0 V, VIH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5112805/HM5113805 -6 Parameter Random read or write cycle time Symbol tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tOED tDZO tDZC tT Min 104 40 10 60 10 0 10 0 10 14 12 15 40 5 15 0 0 2 Max -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4 Notes
5$6 precharge time &$6 precharge time 5$6 pulse width &$6 pulse width
Row address setup time Row address hold time Column address setup time Column address hold time
5$6 to &$6 delay time 5$6 to column address delay time 5$6 hold time &$6 hold time &$6 to 5$6 precharge time 2( to Din delay time 2( delay time from Din &$6 delay time from Din
Transition time (rise and fall)
11
HM5112805 Series, HM5113805 Series
Read Cycle
HM5112805/HM5113805 -6 Parameter Access time from 5$6 Access time from &$6 Access time from address Access time from 2( Read command setup time Read command hold time to &$6 Read command hold time from 5$6 Read command hold time to 5$6 Column address to 5$6 lead time Column address to &$6 lead time Symbol tRAC tCAC tAA tOEA tRCS tRCH tRCHR tRRH tRAL tCAL tCLZ tOH tOHO tOFF tOEZ tCDD tOHR tOFR tWEZ tWED tRDD Min -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 21 13 5 21 13, 21 13 21 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9
&$6 to output in low-Z
Output data hold time Output data hold time from 2( Output buffer turn-off time Output buffer turn-off to 2(
&$6 to Din delay time
Output data hold time from 5$6 Output buffer turn-off to 5$6 Output buffer turn-off to :(
:( to Din delay time 5$6 to Din delay time
12
HM5112805 Series, HM5113805 Series
Write Cycle
HM5112805/HM5113805 -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to 5$6 lead time Write command to &$6 lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Min 0 10 10 15 10 0 10 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
Read-Modify-Write Cycle
HM5112805/HM5113805 -6 Parameter Read-modify-write cycle time Symbol tRWC tRWD tCWD tAWD tOEH Min 140 79 34 49 15 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
5$6 to :( delay time &$6 to :( delay time Column address to :( delay time 2( hold time from :(
Refresh Cycle
HM5112805/HM5113805 -6 Parameter Symbol tCSR tCHR tWRP tWRH tRPC Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
&$6 setup time (CBR refresh cycle) &$6 hold time (CBR refresh cycle) :( setup time (CBR refresh cycle) :( hold time (CBR refresh cycle) 5$6 precharge to &$6 hold time
13
HM5112805 Series, HM5113805 Series
EDO Page Mode Cycle
HM5112805/HM5113805 -6 Parameter EDO page mode cycle time EDO page mode 5$6 pulse width Access time from &$6 precharge Symbol tHPC tRASP tCPA tCPRH tDOH tCOL tCOP tRCHC tWPE tOEP Min 25 -- -- 35 3 10 5 35 10 10 Max -- 100000 35 -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns 9, 22 Notes 20 16 9, 17
5$6 hold time from &$6 precharge Output data hold time from &$6 low &$6 hold time referred 2( &$6 to 2( setup time
Read command hold time from &$6 precharge Write pulse width during &$6 precharge
2( precharge time
EDO Page Mode Read-Modify-Write Cycle
HM5112805/HM5113805 -6 Parameter EDO page mode read-modify-write cycle time Symbol tHPRWC tCPW Min 68 54 Max -- -- Unit ns ns 14 Notes
:( delay time from &$6 precharge
Refresh(HM5112805 Series)
Parameter Refresh period Refresh period (L-version) Symbol tREF tREF Max 64 64 Unit ms ms Notes 8192 cycles 8192 cycles
14
HM5112805 Series, HM5113805 Series
Refresh(HM5113805 Series)
Parameter Refresh period Refresh period (L-version) Symbol tREF tREF Max 64 64 Unit ms ms Notes 4096 cycles 4096 cycles
Self Refresh Mode (L-version)
HM5112805L/HM5113805L -6 Parameter Symbol tRASS tRPS tCHS Min 100 110 -50 Max -- -- -- Unit s ns ns Notes 25 25
5$6 pulse width (self refresh) 5$6 precharge time (self refresh) &$6 hold time (self refresh)
Notes:
1. AC measurements assume tT = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing 5$6-only refresh or &$6-before-5$6 refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, than the access time is controlled exclusively by tCAC. 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that tRCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that tRAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. tDS and tDH are referred to &$6 leading edge in early write cycles and to :( leading edge in delayed write or read-modify-write cycles. 16. tRASP defines 5$6 pulse width in EDO page mode cycles. 17. Access time is determined by the longest among tAA, tCAC and tCPA.
18. In delayed write or read-modify-write cycles, 2( must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
15
HM5112805 Series, HM5113805 Series
20. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode 5$6 cycle (EDO page mode mix cycle (1), (2)), minimum value of &$6 cycle (tCAS + tCP + 2 tT) becomes greater than the specified tHPC (min) value. The value of &$6 cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of 5$6 and &$6. Hold time and turn off time are specified by the timing specifications of later rising edge of 5$6 and &$6 between tOHR and tOH and between tOFR and tOFF.
22. tDOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. Enter self refresh mode within 15.6 s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within exiting from self refresh mode. 15.6s after
24. In case of entering from 5$6-only-refresh, it is necessary to execute CBR refresh before and after self refresh mode according as note 23. 25 At tRASS > 100 s, self refresh mode is activated, and not activated at tRASS < 10 s. It is undefined within the range of 10 s tRASS 100 s. For tRASS 10 s, it is necessary to satisfy tRPS. 26. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL.
16
HM5112805 Series, HM5113805 Series
Timing Waveforms*26
Read Cycle
tRC tRAS RAS tCSH tT tRCD tRSH tCAS tCRP
tRP
CAS tRAD tASR tRAH tASC tRAL tCAL tCAH
Address
Row
Column tRRH tRCHR tRCS tRCH
WE tDZC tWED
tCDD tRDD
Din
High-Z
tDZO
tOEA
tOED
OE tCAC tAA tRAC tCLZ tOEZ tOHO tOFF tOH tOFR tOHR tWEZ Dout Dout
17
HM5112805 Series, HM5113805 Series
Early Write Cycle
tRC tRAS tRP
RAS tCSH tRCD tT CAS tRSH tCAS tCRP
tASR
tRAH
tASC
tCAH
Address
Row
Column
tWCS
tWCH
WE
tDS
tDH
Din
Din
Dout
High-Z*
* t WCS
t WCS (min)
18
HM5112805 Series, HM5113805 Series
Delayed Write Cycle*
18
tRC tRAS
tRP
RAS tCSH tRCD tT CAS tASR tRAH tASC tCAH tRSH tCAS tCRP
Address
Row
Column tCWL tRCS tRWL tWP
WE
tDZC
tDS
tDH
Din
High-Z
Din tOED tOEP
tDZO
tOEH
OE tOEZ tCLZ High-Z Invalid Dout
Dout
19
HM5112805 Series, HM5113805 Series
Read-Modify-Write Cycle*
18
tRWC tRAS RAS tT tRCD tCAS
tRP
tCRP
CAS tRAD tASR tRAH tASC tCAH
Address
Row tRCS
Column tCWD tAWD tRWD tCWL tRWL tWP
WE tDZC tDH
tDS High-Z
Din
Din tOED tOEH
tDZO tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ
20
HM5112805 Series, HM5113805 Series
#$ #$-Only Refresh Cycle
tRC tRAS
RAS
tRP
tT tCRP
CAS
tRPC
tCRP
tASR
Address
tRAH
Row tOFR tOFF
Dout
High-Z

21
HM5112805 Series, HM5113805 Series
$ $-Before-#$ Refresh Cycle #$
tRC tRP tRAS tRP tRAS tRC tRP
RAS tT tRPC tCP tCSR tCHR tRPC tCP tCSR tCHR tCRP
CAS tWRP WE tWRH tWRP tWRH
Address tOFR tOFF Dout High-Z

22
HM5112805 Series, HM5113805 Series
Hidden Refresh Cycle
tRC tRAS tRC tRAS tRC tRP tRAS tRP
tRP
RAS
tT tRSH tRCD tCHR tCRP
CAS
tRAD tASR tRAH tASC tRAL tCAH
Address
Row
Column
tRRH tRCS tRCH
WE
tDZC tWED tCDD tRDD
High-Z Din
tDZO tOEA
tOED
OE
tCAC tAA tRAC tCLZ tOFF tOH tOEZ tWEZ tOHO

Dout Dout
tOFR tOHR
23
HM5112805 Series, HM5113805 Series
EDO Page Mode Read Cycle (1)
t RP
RAS
t RASP tT t CSH t CAS t RCS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC
t HPC t CPRH t CP t t CRP
RSH
CAS
tCAS t RRH t RCH
WE
tASR
Address
tRAH tASC Row
tCAH
t WPE t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL t OEP tOEP tCOP tOED
OE
tOEA tCAC tAA
tCPA tAA tCAC tOEZ tOHO tOEA
tCPA tCPA tAA tCAC tAA tOEZ tCAC
tOFR tOHR tOEZ tOHO tOFF tOH
tWEZ tRAC tDOH tOHO tOEA
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
24
HM5112805 Series, HM5113805 Series
EDO Page Mode Read Cycle (2)
t RP
RAS
t RASP t HPC t CAS tHPC t CP t CAS t RCHC t RCS t CP t HPC tRSH tCAS t RRH t RCH t CRP
tT CAS
t CSH t CAS
t CP
WE
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL
tRDD tCDD
Din
High-Z tDZO tCOL t OEP tOEP tCOP tOED
OE
tOEA tCAC tAA
tCPA tAA tCAC tOEZ tOHO

tOEZ tRAC tDOH tOEA tCAC tDOH tOHO tOEA
Dout
tCPA tAA tCAC
tCPA tAA
tOFR tOHR tOEZ tOHO tOFF tOH
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
25
HM5112805 Series, HM5113805 Series
EDO Page Mode Early Write Cycle
tRASP tRP
RAS tT tRCD CAS
tCSH tCAS tCP
tHPC tCAS tCP
tRSH tCAS tCRP
tASR
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
Address
Row
Column 1
Column 2
Column N
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
WE
tDS
tDH
tDS
tDH
tDS
tDH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
26
HM5112805 Series, HM5113805 Series
EDO Page Mode Delayed Write Cycle*
18
tRASP tRP RAS tT tCSH tRCD CAS tRAD tASR tRAH Address Row tASC tCAH Column 1 tCWL tRCS WE tWP tDZC tDS tDH Din tDZO tOED tOEP tOEH OE Din 1 tDZO tWP tDZC tDS tDH Din 2 tOED tOEP tOEH tDZO tWP tDZC tDS tDH Din N tOED tOEP tOEH tRCS tASC tCAH Column 2 tCWL tRCS tASC tCAH Column N tCWL tRWL tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP

tCLZ tCLZ tCLZ tOEZ tOEZ Dout Invalid Dout Invalid Dout Invalid Dout
tOEZ High-Z
27
HM5112805 Series, HM5113805 Series
EDO Page Mode Read-Modify-Write Cycle*
18
t RASP t RP RAS tT t CP t RCD
CAS
t HPRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO t OED t OEP t OEH Din 1 t DZO t OED t OEP t OEH t WP t DZC t DS t DH Din 2 t DZO t OED t OEP t OEH t WP t DZC t DS t DH Din N t CWL t RCS t ASC t CAH Column 2 t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
OE t OHO t OHO t OHO t OEA t CAC t OEA t CAC t OEA t CAC

t AA t RAC t AA t CPA t AA t CPA t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
28
HM5112805 Series, HM5113805 Series
EDO Page Mode Mix Cycle (1)*
20
t RP RAS tT CAS t CAS t CSH t RCD t WCS WE t ASC tRAH Row t WCH t RCS tCPW tAWD tCAH t ASC t CAH Column 2 t CAL t DS
Din
t RASP t CRP tCAS tCWL t RCS tWP t RAL t CAH Column 4 t CAL t DS High-Z tOED t DH Din 3 tOEP tWED tRDD tCDD tRSH t RRH t RCH
t CP t CAS
t CP tCAS
t CP
tASR Address
tASC t CAH Column 3
tASC
Column 1
t DH Din 1
OE tCPA tAA tOEA tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH tCAC t DOH tCAC t OHO tOEA
Dout
Dout 2
Dout 3
Dout 4
29
HM5112805 Series, HM5113805 Series
EDO Page Mode Mix Cycle (2) *
20
t RP
RAS
t RASP
tT CAS
t CSH t CAS t RCD t RCS t RCHR
t CP t CAS
t CP tCAS tCWL t RCS tCPW
t CP tCAS t RCS tWP t RAL tASC t CAH Column 4 t CAL t DS tRSH
t CRP
t RCH
tWCS t WCH
t RRH t RCH
WE
tASR
Address
t ASC tRAH Row
tCAH
t ASC t CAH Column 2
t ASC t CAH Column 3
Column 1 t CAL
t DS
Din
t DH Din 2
t DH Din 3 t OEP tOED tCOL tCOP
tRDD tCDD
High-Z
t OEP tOED
OE
tWED
tAA tOEA tCAC tRAC t OHO
Dout
t OEA tOEZ tCPA tAA tCAC tOEZ t OHO
Dout 3
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout 1
30
HM5112805 Series, HM5113805 Series
Self Refresh Cycle (L-version)*
tRP
23, 24, 25
tRASS
tRPS
RAS tRPC tCP CAS tWRP tWRH tT tCRP tCSR tCHS
WE tOFR tOFF

Dout High-Z
31
HM5112805 Series, HM5113805 Series
Package Dimensions
HM5112805TD/LTD Series HM5113805TD/LTD Series (TTP-32DF)
Unit: mm 20.95 21.35 Max 32 17
1 0.42 0.08 0.40 0.06 1.15 Max
1.27 0.21
M
16 0.80
10.16
0.10
0.12 0.05 0.10 0.04
0.05 0.05
0 - 5
1.20 Max
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-32DF -- -- 0.54 g
32
0.45
11.76 0.20
0.50 0.10
HM5112805 Series, HM5113805 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
33
HM5112805 Series, HM5113805 Series
Revision Record
Rev. 0.0 0.1 Date Oct. 13, 1997 Jan. 28, 1998 Contents of Modification Initial issue Deletion of HM5112805L Series Deletion of HM5112805TD/LTD-5 Addition of HM5113805TD-6 Series Deletion of Self refresh cycle 1.0 2.0 Apr. 3, 1998 Jul. 10, 1998 Capacitance CI/O max: 7 pF to 8 pF Addition of HM5112805LTD-6 Series Addition of HM5113805LTD-6 Series PKG code TTP-32DE to TTP-32DF DC Characteristics Addition of ICC2, ICC10, ICC11 Addition of note 4 AC Characteristics Addition of tREF (L-version): 64 ms Addition of self refresh mode Addition of notes 23 to 25 Timing waveforms EDO page mode mix cycle (1), (2) Addition of self refresh cycle (L-version) Package Dimensions Change leader line of terminal length M. Kawamura Y. Takahashi Drawn by Approved by M. Kawamura Y. Takahashi M. Kawamura Y. Takahashi
34

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